SH7706 Datasheet, PDF (173/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 6 Interrupt Controller (INTC)
6.4.2 Interrupt Control Register 0 (ICR0)
The interrupt control register 0 (ICR0) is a 16-bit register that sets the input signal detection mode
of the external interrupt input pin NMI and indicates the input signal level to the NMI pin. This
register is initialized to H'0000 at power-on reset or manual reset, but is not initialized in standby
mode.
Bit
Bit Name Initial Value R/W Description
15
NMIL
0/1*
R NMI Input Level
Sets the level of the signal input at the NMI pin. This
bit can be read to determine the NMI pin level. This bit
cannot be modified.
0: NMI input level is low
1: NMI input level is high
14 to 9 —
All 0
R Reserved
These bits are always read as 0. The write value
should always be 0.
8
NMIE
0
R/W NMI Edge Select
Selects whether the interrupt request signal is
detected on the falling or rising edge of NMI input.
0: Interrupt request signal is detected on falling edge
of NMI input
1: Interrupt request signal is detected on rising edge
of NMI input
7 to 0 —
All 0
R Reserved
These bits are always read as 0. The write value
should always be 0.
Note: * When NMI input is high: 1; when NMI input is low: 0.
Rev. 5.00 May 29, 2006 page 125 of 698
REJ09B0146-0500