SH7706 Datasheet, PDF(142/749 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

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SH7706 Datasheet, PDF (142/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

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Section 4 Exception Processing

ï£§ Operations: The virtual address (32 bits) that caused the exception is set in TEA. The PC

and SR of the instruction that generated the exception are saved to the SPC and SSR,

respectively. If the exception occurred during a read, H'0E0 is set in EXPEVT; if the

exception occurred during a write, H'100 is set in EXPEVT. The BL, MD, and RB bits in

SR are set to 1 and a branch occurs to PC = VBR + H'0100. Refer to section 3.5.5,

Processing Flow in Event of MMU Exception (Same Processing Flow for CPU Address

Error).

â¢ Unconditional trap

ï£§ Conditions: TRAPA instruction executed

ï£§ Operations: The exception is a processing-completion type, so the PC of the instruction

after the TRAPA instruction is saved to the SPC. SR from the time when the TRAPA

instruction was executing is saved to SSR. The 8-bit immediate value in the TRAPA

instruction is quadrupled and set in TRA (9 to 0). H'160 is set in EXPEVT. The BL, MD,

and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100.

â¢ General illegal instruction exception

ï£§ Conditions: When corresponded to the following items.

A. When undefined code not in a delay slot is decoded

Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S

Undefined instruction: H'Fxxx.(In the case of SR.CL = 1, the value should be

B'111111xxxxxxxxxx.)

B. When a privileged instruction not in a delay slot is decoded in user mode

Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR

with LDC/STC are not privileged instructions.

ï£§ Operations: The PC and SR of the instruction that generated the exception are saved to the

SPC and SSR, respectively. H'180 is set in EXPEVT. The BL, MD, and RB bits in SR are

set to 1 and a branch occurs to PC = VBR + H'0100. When an undefined instruction other

than H'Fxxx is decoded, operation cannot be guaranteed.

â¢ Illegal slot instruction exception

ï£§ Conditions: When corresponded to the following items.

A. When undefined code in a delay slot is decoded

Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S

Undefined instruction: H'Fxxx. (In the case of SR.CL = 1, the value should be

B'111111xxxxxxxxxx.)

B. When an instruction that rewrites the PC in a delay slot is decoded

Instructions that rewrite the PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,

BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR

Rev. 5.00 May 29, 2006 page 94 of 698

REJ09B0146-0500

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