SH7706 Datasheet, PDF (14/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Item
Page
9.5.2 Register
294
Description
Compare Match Timer
Control/Status
Register (CMCSR)
9.5.3 Operation
295
Period Count
Operation
CMCNT Count Timing 296
Figure 9.28 Count
Timing
Revision (See Manual for Details)
Description amended
The compare match timer control/status register (CMCSR) is a
16-bit register that indicates the occurrence of compare
matches,
and establishes the clock used for
incrementation.
Table amended
Bit
Bit Name Initial Value R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Description
Clock select 1 and 0
These bits select the clock input to the CMCNT
from among the four clocks obtained by dividing
the peripheral clock (Pφ). When the STR0 bit of
the CMSTR is set to 1, the CMCNT begins
incrementing with the clock selected by CKS1 and
CKS0.
00: P φ/4
01: P φ/8
10: P φ/16
11: P φ/64
Description amended
When a clock is selected with the CKS1 and CKS0 bits of the
CMCSR register and the STR0 bit of the CMSTR is set to 1, the
CMCNT begins incrementing with the selected clock. ...
Description amended
One of four clocks (Pφ/4, Pφ/8, Pφ/16, Pφ/64) obtained by
dividing the peripheral clock (Pφ) can be selected by the CKS1
and CKS0 bits of the CMCSR. Figure 9.28 shows the timing.
Figure amended
Peripheral clock (Pφ)
CMT clock
CMCNT0 input clock
CMCNT0
N-1
Rev. 5.00 May 29, 2006 page xiv of xlviii