SH7706 Datasheet, PDF (667/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 24 Electrical Characteristics
24.3.2 Control Signal Timing
Table 24.6 Control Signal Timing
Item
Symbol Min
Max
Unit Figure
RESETP pulse width
RESETP setup time^*1
RESETP hold time
RESETM pulse width
RESETM setup time
RESETM hold time
BREQ setup time
BREQ hold time
NMI setup time^*1
NMI hold time
IRQ5 to IRQ0 setup time^*1
t_RESPW
t
RESPS
t_RESPH
t_RESMW
t_RESMS
t_RESMH
t
BREQS
t
BREQH
t_NMIS
t_NMIH
t_IRQS
20^*3
—
20
—
2
—
12^*4
—
6
—
34
—
6
—
4
—
10
—
4
—
10
—
tcyc
24.11,
ns
24.12
ns
tcyc
ns
ns
ns
24.14
ns
ns
24.12,
ns
24.13
ns
IRQ5 to IRQ0 hold time
t
4
IRQH
—
ns
IRQOUT delay time
t
—
10
ns
IRQOD
BACK delay time
t_BACKD
—
10
ns
24.14,
STATUS1, STATUS0 delay time
t_STD
—
10
ns
24.15
Bus tri-state delay time 1
t_BOFF1
0
15
ns
Bus tri-state delay time 2
t
0
BOFF2
15
ns
Bus buffer-on time 1
t
0
BON1
15
ns
Bus buffer-on time 2
t_BON2
0
15
ns
Notes: 1. RESETP, NMI, and IRQ5 to IRQ0 are asynchronous. Changes are detected at the
clock fall when the setup shown is used. When the setup cannot be used, detection can
be delayed until the next clock falls.
2. The upper limit of the external bus clock is 66 MHz.
3. In the standby mode, when XTAL oscillation continues, t_RESPn = t_OSC1 (100µs), when XTAL
oscillation stops, t = t (10 ms). In the sleep mode, t = t (100 µs).
RESPW
OSC2
RESPW
PLL1
When the clock multiplication ratio is changed, t_RESPW = t_PLL1 (100 µs).
4. In the standby mode, t_RESMW = t_OSC2 (10 ms). In the sleep mode, RESETM must be kept
low until STATUS (0, 1) changes to reset (HH). When the clock multiplication ratio is
changed, RESETM must be kept low until STATUS (0, 1) changes to reset (HH).
Rev. 5.00 May 29, 2006 page 619 of 698
REJ09B0146-0500