SH7706 Datasheet, PDF (178/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 6 Interrupt Controller (INTC)
Bit
Bit Name Initial Value R/W Description
2
IRQ2R 0
R/W IRQ2 Interrupt Request
Indicates whether an interrupt request is input to the
IRQ2 pin. When edge detection mode is set for IRQ2,
an interrupt request is cleared by clearing the IRQ2R
bit. It is not necessary to clear the flag when using
level-sensing, because this bit merely shows the status
of the IRQ2 pin.
0: An interrupt request is not input to IRQ2 pin
1: An interrupt request is input to IRQ2 pin
1
IRQ1R 0
R/W IRQ1 Interrupt Request
Indicates whether an interrupt request is input to the
IRQ1 pin. When edge detection mode is set for IRQ1,
an interrupt request is cleared by clearing the IRQ1R
bit. It is not necessary to clear the flag when using
level-sensing, because this bit merely shows the status
of the IRQ1 pin.
0: An interrupt request is not input to IRQ1 pin
1: An interrupt request is input to IRQ1 pin
0
IRQ0R 0
R/W IRQ0 Interrupt Request (IRQ0R)
Indicates whether an interrupt request is input to the
IRQ0 pin. When edge detection mode is set for IRQ0,
an interrupt request is cleared by clearing the IRQ0R
bit. It is not necessary to clear the flag when using
level-sensing, because this bit merely shows the status
of the IRQ0 pin.
0: An interrupt request is not input to IRQ0 pin
1: An interrupt request is input to IRQ0 pin
Rev. 5.00 May 29, 2006 page 130 of 698
REJ09B0146-0500