SH7706 Datasheet, PDF (300/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
• Reload function: The value that was specified in the source address register can be
automatically reloaded every 4 DMA transfers. This function is only valid in channel 2.
• Three types of Transfer requests
 External request: From two DREQ pins (channels 0 and 1 only). DREQ can be detected
either by the falling edge or by the low level.
 On-chip module request: Requests from on-chip peripheral modules such as serial
communications interface (SCIF), A/D converter (A/D), and a timer (CMT). This request
can be accepted in all the channels.
 Auto request: The transfer request is generated automatically within the DMAC.
• Selectable bus modes: Cycle-steal mode or burst mode
• Selectable channel priority levels
 Fixed mode: The channel priority is fixed.
 Round-robin mode: The priority of the channel in which the execution request was
accepted is made the lowest.
• Interrupt request: An interrupt request can be generated to the CPU after transfers end by the
specified counts.
Rev. 5.00 May 29, 2006 page 252 of 698
REJ09B0146-0500