SH7706 Datasheet, PDF (616/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 22 Power-Down Modes
Table 22.1 Power-Down Modes
State
Mode
Transition
Conditions
CPU
On-Chip
Reg- On-Chip Peripheral
External Canceling
CPG CPU ister Memory Modules Pins Memory Procedure
Sleep
mode
Software
standby
mode
Module
standby
function
Execute SLEEP
instruction with
STBY bit cleared
to 0 in STBCR
Runs
Halts
Held
Execute SLEEP
instruction with
STBY bit set to 1
in STBCR
Halts
Halts
Held
Set MSTP bit of Runs Runs Held
STBCR to 1^*5
*⁴
Held
Held
Held
Hardware Drive CA pin low Halts Halts Held Held
standby
mode
Runs
Held Refresh 1. Interrupt
2. Reset
Halts^*1
Held Self-
refresh
1. Interrupt
2. Reset
Specified
module
halts
Halts^*3
*²
Refresh
Held Self-
refresh
1. Clear MSTP
bit to 0
2. Power-on
reset
Power-on reset
Notes: 1. The RTC still runs if the START bit in RCR2 is set to 1 (see section 13, Realtime Clock
(RTC)). TMU still runs when output of the RTC is used as input to its counter (see
section 12, Timer Unit (TMU)).
2. Depends on the on-chip supporting module.
TMU external pin: Held
SCI external pin: Reset
3. The RTC still runs if the START bit in RCR2 is set to 1. TMU does not run.
4. When the LSI enters sleep mode, the CPU halts.
5. If the realtime clock (RTC) is set to module standby mode (bit 1 in standby control
register (STBCR) set to 1) before any register in the RTC, SCI, or TMU is accessed,
registers in the serial communication interface (SCI) or timer unit (TMU) may not be
read properly. To avoid this problem, access (read or write) any register in the RTC,
SCI, or TMU once or more before setting the RTC to module standby mode.
Rev. 5.00 May 29, 2006 page 568 of 698
REJ09B0146-0500