SH7706 Datasheet, PDF (263/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Table 8.18 Example of Correspondence between this LSI and Synchronous DRAM
Address Pins (AMX (3 to 0) = 0100 (32-Bit Bus Width))
Address Pin of this LSI
RAS Cycle
CAS Cycle
A15
A23
A23
A14
A22
A22
A13
A21
A13
A12
A20
L/H
A11
A19
A11
A10
A18
A10
A9
A17
A9
A8
A16
A8
A7
A15
A7
A6
A14
A6
A5
A13
A5
A4
A12
A4
A3
A11
A3
A2
A10
A2
A1
A9
A1
A0
A8
A0
Synchronous DRAM Address Pin
Function
A13(BA1) BANK select address
A12(BA0)
A11
Address
A10
Address/precharge setting
A9
Address
A8
A7
A6
A5
A4
A3
A2
A1
A0
Not used
Not used
Burst Read
Figure 8.13 shows the timing chart for a burst read. In the example below, it is assumed that four
2M × 8-bit synchronous DRAMs are connected and a 32-bit data width is used, and the burst
length is 1. Following the Tr cycle in which ACTV command output is performed, a READ
command is issued in the Tc1, Tc2, and Tc3 cycles, and a READA command in the Tc4 cycle, and
the read data is accepted on the rising edge of the external command clock (CKIO) from cycle Td1
to cycle Td4. The Tpc cycle is used to wait for completion of auto-precharge based on the
READA command inside the synchronous DRAM; no new access command can be issued to the
same bank during this cycle, but access to synchronous DRAM for another area is possible. In the
this LSI, the number of Tpc cycles is determined by the TPC bit specification in MCR, and
commands cannot be issued for the same synchronous DRAM during this interval.
Rev. 5.00 May 29, 2006 page 215 of 698
REJ09B0146-0500