SH7706 Datasheet, PDF (516/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.10 FIFO Data Count Set Register 2 (SCFDR2)
The SCFDR2 is a 16-bit register which indicates the number of data stored in the SCFTDR2 and
SCFRDR2. The SCFDR2 is always read from the CPU.
The upper eight bits of this register indicate the number of transmit data items stored in the
SCFTDR2 that have not yet been transmitted. The H'00 means no transmit data, and the H'10
means that the full of transmit data are stored in the SCFTDR2.
The lower eight bits of this register indicate the number of receive data items stored in the
SCFRDR2. The H'00 means no receive data, and the H'10 means that the full of receive data are
stored in the SCFRDR2.
Bit
Bit Name Initial Value R/W
15 to 13 —
All 0
R
12 to 8 T4 to T0 All 0
R
7 to 5 —
All 0
R
4 to 0 R4 to R0 All 0
R
Description
Reserved
These bits are always read as 0.
Number of non-transmitted data.
Reserved
These bits are always read as 0.
Number of received data.
16.3.11 SC Port Control Register (SCPCR)
For information about the SC port control register (SCPCR), see section 14.3.8, SC Port Control
Register (SCPCR).
16.3.12 SC Port Data Register (SCPDR)
For information about the SC port data register (SCPDR), see section 14.3.9, SC Port Data
Register (SCPDR).
Rev. 5.00 May 29, 2006 page 468 of 698
REJ09B0146-0500