SH7706 Datasheet, PDF (213/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
8.2 Input/Output Pin
Table 8.1 lists the BSC pin configuration.
Table 8.1 Pin Configuration
Pin Name
Address bus
Data bus
Bus cycle start
Signal
I/O
A25 to A0
O
D15 to D0
I/O
D31 to D16
I/O
BS
O
Chip select 0, 2 to 4 CS0, CS2 to O
CS4
Chip select 5, 6
CS5/CE1A,
O
CS6/CE1B
PCMCIA card
select
Read/write
CE2A, CE2B O
RD/WR
O
Row address strobe RASL
O
L
Row address strobe RASU
O
U
Column address
CASL
O
strobe
Column address
CASU
O
strobe
Data enable 0
WE0/DQMLL O
Data enable 1
WE1/DQMLU/ O
WE
Description
Address output
Data I/O
When 32-bit bus width, data I/O
Shows start of bus cycle. During burst transfers,
asserts every data cycle.
Chip select signal to indicate area being accessed.
Chip select signal to indicate area being accessed.
CS5/CE1A and CS6/CE1B can also be used as
CE1A and CE1B of PCMCIA.
When PCMCIA is used, CE2A and CE2B
Data bus direction indicator signal. Synchronous
DRAM write indicator signal.
When synchronous DRAM is used, RASL for
lower 32-Mbyte address.
When synchronous DRAM is used, RASU for
upper 32-Mbyte address.
When synchronous DRAM is used, CASL signal
for lower 32-Mbyte address.
When synchronous DRAM is used, CASU signal
for upper 32-Mbyte address.
When memory other than synchronous DRAM is
used, selects D7 to D0 write strobe signal. When
synchronous DRAM is used, selects D7 to D0.
When memory other than synchronous DRAM is
used, selects D15 to D8 write strobe signal. When
synchronous DRAM is used, selects D15 to D8.
When PCMCIA is used, strobe signal that
indicates the write cycle.
Rev. 5.00 May 29, 2006 page 165 of 698
REJ09B0146-0500