SH7706 Datasheet, PDF (582/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 19 A/D Converter (ADC)
Bit Bit Name Initial Value R/W
5
ADST
0
R/W
4
MULTI
0
R/W
3
CKS
0
R/W
Description
A/D Start
Starts or stops A/D conversion. The ADST bit
remains set to 1 during A/D conversion. It can also
be set to 1 by external trigger input at the ADTRG
pin.
0: A/D conversion is stopped
1: 1. Single mode: A/D conversion starts; ADST is
automatically cleared to 0 when conversion
ends.
2. Multi mode: A/D conversion stauts: ADST is
automatically cleard to 0 when conversion
ends in all selected channels.
3. Scan mode: A/D conversion starts and
continues, cycling among the selected
channels, until ADST is cleared to 0 by
software reset, or by a transition to standby
mode.
Multi Mode
Selects single mode, multi mode or scan mode.
For further information on operation in these
modes, see section 19.6, Operation. The mode is
selected by the combination of this bit (MULTI)
and bit 5 (SCN) of ADCR.
MULTI
0
0
1
1
SCN
0
1
0
1
: Single mode
: Single mode
: Multi mode
: Scan mode
Clock Select
Selects the A/D conversion time. Clear the ADST
bit to 0 before switching the conversion time.
0: Conversion time = 536 states (maximum)
1: Conversion time = 266 states (maximum)^*2
Rev. 5.00 May 29, 2006 page 534 of 698
REJ09B0146-0500