SH7706 Datasheet, PDF (136/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 4 Exception Processing
4.2.2 Interrupt Event Register (INTEVT)
The interrupt event register (INTEVT) contains a 12-bit interrupt exception code or a code
indicating the interrupt priority. Which is set when an interrupt occurs depends on the interrupt
source (refer to section 6, Interrupt Controller (INTC)). The exception code or interrupt priority
code is set automatically by hardware when an exception occurs. INTEVT can also be modified by
software.
Bit
31 to 12
11 to 0
Bit Name


Initial Value R/W
All 0
R

R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
12-bit interrupt exception code or a code indicating
the interrupt priority
4.2.3 Interrupt Event Register 2 (INTEVT2)
The interrupt event register 2 (INTEVT2) contains a 12-bit exception code. The exception code set
in INTEVT2 is that for an interrupt request. The exception code is set automatically by hardware
when an exception occurs.
Bit
31 to 12
11 to 0
Bit Name


Initial Value R/W
All 0
R

R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
12-bit exception code
Rev. 5.00 May 29, 2006 page 88 of 698
REJ09B0146-0500