SH7706 Datasheet, PDF (431/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 14 Serial Communication Interface (SCI)
14.3.10 Bit Rate Register (SCBRR)
The bit rate register (SCBRR) is an eight-bit register that, together with the baud rate generator
clock source selected by the CKS1 and CKS0 bits in SCSMR, determines the serial
transmit/receive bit rate.
The CPU can always read and write the SCBRR. The SCBRR is initialized to H'FF by a reset or in
module standby or standby mode. Each channel has independent baud rate generator control, so
different values can be set in two channels.
The SCBRR setting is calculated as follows:
Asynchronous mode: N = [Pφ/(64 × 2^{2n – 1} × B)] × 10⁶ – 1
Clock synchronous mode: N = [Pφ/(8 × 2^{2n – 1} × B)] × 10⁶ – 1
B: Bit rate (bit/s)
N: SCBRR setting for baud rate generator (0 ≤ N ≤ 255)
Pφ: Operating frequency for peripheral modules (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of
n, see table 14.2.)
Table 14.2 SCSMR Settings
n
Clock Source
0
Pφ
1
Pφ/4
2
Pφ/16
3
Pφ/64
CKS1
0
0
1
1
SCSMR Settings
CKS0
0
1
0
1
Find the bit rate error for the asynchronous mode by the following formula:
Error (%) =
Pφ × 10⁶
(N + 1) × B × 64 × 2^{2n−1 − 1 × 100}
Rev. 5.00 May 29, 2006 page 383 of 698
REJ09B0146-0500