SH7706 Datasheet, PDF (214/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Pin Name
Data enable 2
Signal
I/O
WE2/DQMUL/ O
ICIORD
Data enable 3
WE3/DQMUU/ O
ICIOWR
Read
RD
O
Wait
WAIT
I
Clock enable
CKE
O
IOIS16
IOIS16
I
Bus release request BREQ
I
Bus release
BACK
O
acknowledgment
Description
When memory other than synchronous DRAM is
used, selects D23 to D16 write strobe signal.
When synchronous DRAM is used, selects D23 to
D16. When PCMCIA is used, strobe signal
indicating I/O read.
When memory other than synchronous DRAM is
used, selects D31 to D24 write strobe signal.
When synchronous DRAM is used, selects D31 to
D24. When PCMCIA is used, strobe signal
indicating I/O write.
Strobe signal indicating read cycle
Wait state request signal
Clock enable control signal of synchronous DRAM
Signal indicating PCMCIA 16-bit I/O. Valid only in
little-endian mode.
Bus release request signal
Bus release acknowledge signal
8.3 Area Overview
Space Allocation: In the architecture of this LSI, both logical spaces and physical spaces have 32-
bit address spaces. The logical space is divided into five areas by the value of the upper bits of the
address. The physical space is divided into eight areas.
Logical space can be allocated at physical spaces using a memory management unit (MMU). For
details, refer to section 3, Memory Management Unit (MMU), which describes area allocation for
physical spaces.
As listed in table 8.2, this LSI can be connected directly to six areas of memory/PCMCIA
interface, and it outputs chip select signals (CS0, CS2 to CS6, CE2A, CE2B) for each of them.
CS0 is asserted during area 0 access; CS6 is asserted during area 6 access. When PCMCIA
interface is selected in area 5 or 6, in addition to CS5/CS6, CE2A/CE2B are asserted for the
corresponding bytes accessed.
Rev. 5.00 May 29, 2006 page 166 of 698
REJ09B0146-0500