SH7706 Datasheet, PDF (381/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 12 Timer Unit (TMU)
12.4.1 Counter Operation
When the STR0 to STR2 bits in TSTR are set to 1, the corresponding timer counter (TCNT) starts
counting. When a TCNT underflows, the UNF flag of the corresponding timer control register
(TCR) is set. At this time, if the UNIE bit in TCR is 1, an interrupt request is sent to the CPU.
Also at this time, the value is copied from TCOR to TCNT and the down-count operation is
continued.
An example of the count operation setting flow
The count operation is shown in figure 12.2.
Select operation
Select counter
clock
Set underflow
interrupt generation
Set timer constant
register
Initialize timer
counter
Start counting
(1)
(2)
When using input
capture function
Set interrupt
generation
(3)
(4)
(5)
(6)
(1) Select the counter clock with the TPSC0-TPSC2
bits in the timer control register. If the external
clock is selected, set the TCLK pin to input mode
with the TOCE bit in TOCR, and select its edge
with the CKEG1 and CKEG0 bits in the timer
control register.
(2) Use the UNIE bit in the timer control register to set
whether to generate an interrupt when timer
counter underflows.
(3) When using the input capture function, set the
ICPE bits in the timer control register, including
the choice of whether or not to use the interrupt
function (channel 2 only).
(4) Set a value in the timer constant register
(the cycle is the set value plus 1).
(5) Set the initial value in the timer counter.
(6) Set the STR bit in the timer start register to 1 to
start operation.
Note: When an interrupt has been generated, clear the flag in the interrupt handler that caused it.
If interrupts are enabled without clearing the flag, another interrupt will be generated.
Figure 12.2 Setting the Count Operation
Rev. 5.00 May 29, 2006 page 333 of 698
REJ09B0146-0500