SH7706 Datasheet, PDF (36/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 6 Interrupt Controller (INTC)
Figure 6.1 INTC Block Diagram........................................................................................... 114
Figure 6.2 Example of IRL Interrupt Connection ................................................................. 117
Figure 6.3 Interrupt Operation Flowchart ............................................................................. 134
Figure 6.4 Example of Pipeline Operations when IRL Interrupt Is Accepted....................... 138
Section 7 User Break Controller
Figure 7.1 Block Diagram of User Break Controller ............................................................ 140
Section 8 Bus State Controller (BSC)
Figure 8.1 BSC Functional Block Diagram .......................................................................... 164
Figure 8.2 Corresponding to Logical Address Space and Physical Address Space .............. 167
Figure 8.3 Physical Space Allocation.................................................................................... 169
Figure 8.4 PCMCIA Space Allocation.................................................................................. 170
Figure 8.5 Basic Timing of Basic Interface........................................................................... 206
Figure 8.6 Example of 32-Bit Data-Width Static RAM Connection..................................... 207
Figure 8.7 Example of 16-Bit Data-Width Static RAM Connection..................................... 208
Figure 8.8 Example of 8-Bit Data-Width Static RAM Connection....................................... 208
Figure 8.9 Basic Interface Wait Timing (Software Wait Only) ............................................ 209
Figure 8.10 Basic Interface Wait State Timing
(Wait State Insertion by WAIT Signal WAITSEL = 1)....................................... 210
Figure 8.11 Example of 64-Mbit Synchronous DRAM Connection (32-Bit Bus Width) ....... 212
Figure 8.12 Example of 64-Mbit Synchronous DRAM (16-Bit Bus Width) .......................... 213
Figure 8.13 Basic Timing for Synchronous DRAM Burst Read............................................. 216
Figure 8.14 Synchronous DRAM Burst Read Wait Specification Timing.............................. 217
Figure 8.15 Basic Timing for Synchronous DRAM Single Read ........................................... 218
Figure 8.16 Basic Timing for Synchronous DRAM Burst Write ............................................ 219
Figure 8.17 Basic Timing for Synchronous DRAM Single Write .......................................... 220
Figure 8.18 Burst Read Timing (No Precharge) ..................................................................... 223
Figure 8.19 Burst Read Timing (Same Row Address) ............................................................ 224
Figure 8.20 Burst Read Timing (Different Row Addresses) ................................................... 225
Figure 8.21 Burst Write Timing (No Precharge)..................................................................... 226
Figure 8.22 Burst Write Timing (Same Row Address) ........................................................... 227
Figure 8.23 Burst Write Timing (Different Row Addresses) .................................................. 228
Figure 8.24 Auto-Refresh Operation....................................................................................... 229
Figure 8.25 Synchronous DRAM Auto-Refresh Timing ........................................................ 230
Figure 8.26 Synchronous DRAM Self-Refresh Timing .......................................................... 231
Figure 8.27 Synchronous DRAM Mode Write Timing........................................................... 233
Figure 8.28 Burst ROM Wait Access Timing ......................................................................... 235
Figure 8.29 Burst ROM Basic Access Timing ........................................................................ 236
Figure 8.30 PCMCIA Space Allocation.................................................................................. 237
Rev. 5.00 May 29, 2006 page xxxvi of xlviii