SH7706 Datasheet, PDF (268/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Single Write
The basic timing chart for write access is shown in figure 8.17. In a single write operation,
following the Tr cycle in which ACTV command output is performed, a WRITA command that
performs auto-precharge is issued in the Tc1 cycle. In the write cycle, the write data is output at
the same time as the write command. In case of the write with auto-precharge command,
precharging of the relevant bank is performed in the synchronous DRAM after completion of the
write command, and therefore no command can be issued for the same bank until precharging is
completed. Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle
Trwl is also added as a wait interval until precharging is started following the write command.
Issuance of a new command for the same bank is postponed during this interval. The number of
Trwl cycles can be specified by the TRWL bit in MCR.
CKIO
Address
upper bits
A12 or A11^*1
Address
lower bits^*2
CSn
RD/WR
RASx
CASx
DQMxx
Tr
Tc1
(Trwl)
(Tpc)
D31 to D0
BS
CKE
Notes: 1. Command bit
2. Column address
Figure 8.17 Basic Timing for Synchronous DRAM Single Write
Rev. 5.00 May 29, 2006 page 220 of 698
REJ09B0146-0500