SH7706 Datasheet, PDF (167/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 6 Interrupt Controller (INTC)
6.3.5 Interrupt Exception Processing and Priority
Tables 6.3 and 6.4 lists the codes for the interrupt event register (INTEVT and INTEVT2), and the
order of interrupt priority. Each interrupt source is assigned unique code. The start address of the
interrupt service routine is common to each interrupt source. This is why, for instance, the value of
INTEVT or INTEVT2 is used as offset at the start of the interrupt service routine and branched to
identify the interrupt source.
The order of priority of the on-chip peripheral module, IRQ, and PINT interrupts is set within the
priority levels 0 to 15 at will by using the interrupt priority level set to registers A to E (IPRA to
IPRE). The order of priority of the on-chip peripheral module, IRQ, and PINT interrupts is set to
zero by RESET.
When the order of priorities for multiple interrupt sources are set to the same level and such
interrupts are generated at the same time, they are processed according to the default order listed
in tables 6.3 and 6.4.
Table 6.3 Interrupt Exception Handling Sources and Priority (IRQ Mode)
Interrupt Source
NMI
H-UDI
IRQ
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
DMAC DEI0
DEI1
DEI2
DEI3
SCIF ERI2
(SCI2) _RXI2
BRI2
TXI2
INTEVT Code
(INTEVT2 Code)
H'1C0 (H'1C0)
H'5E0 (H'5E0)
H'200 to 3C0* (H'600)
H'200 to 3C0* (H'620)
H'200 to 3C0* (H'640)
H'200 to 3C0* (H'660)
H'200 to 3C0* (H'680)
H'200 to 3C0* (H'6A0)
H'200 to 3C0* (H'800)
H'200 to 3C0* (H'820)
H'200 to 3C0* (H'840)
H'200 to 3C0* (H'860)
H'200 to 3C0* (H'900)
H'200 to 3C0* (H'920)
H'200 to 3C0* (H'940)
H'200 to 3C0* (H'960)
Interrupt
Priority
(Initial Value)
IPR (Bit
Numbers)
Priority
within IPR Default
Setting Unit Priority
16
—
—
High
15
—
—
0 to 15 (0)
IPRC (3 to 0) —
0 to 15 (0)
IPRC (7 to 4) —
0 to 15 (0)
IPRC (11 to 8) —
0 to 15 (0)
IPRC (15 to 12) —
0 to 15 (0)
IPRD (3 to 0) —
0 to 15 (0)
IPRD (7 to 4) —
0 to 15 (0)
IPRE (15 to 12) High
0 to 15 (0)
IPRE (7 to 4)
Low
High
Low
Low
Rev. 5.00 May 29, 2006 page 119 of 698
REJ09B0146-0500