SH7706 Datasheet, PDF (357/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 10 Clock Pulse Generator (CPG)
Clock
Mode FRQCR^*1 PLL1
PLL2
Clock Rate^*2
CKIO Frequency
(I:B:P)
Input Frequency Range Range
7
H'0100 ON (× 1) OFF
1:1:1
25 MHz to 33.34 MHz 25 MHz to 33.34 MHz
H'0101 ON (× 1) OFF
1:1:1/2
25 MHz to 66.67 MHz 25 MHz to 66.67 MHz
H'0102 ON (× 1) OFF
1:1:1/4
25 MHz to 66.67 MHz 25 MHz to 66.67 MHz
H'0111 ON (× 2) OFF
2:1:1
25 MHz to 33.34 MHz 25 MHz to 33.34 MHz
H'0112 ON (× 2) OFF
2:1:1/2
25 MHz to 66.67 MHz 25 MHz to 66.67 MHz
H'0115 ON (× 2) OFF
1:1:1
25 MHz to 33.34 MHz 25 MHz to 33.34 MHz
H'0116 ON (× 2) OFF
1:1:1/2
25 MHz to 66.67 MHz 25 MHz to 66.67 MHz
H'0122 ON (× 4) OFF
4:1:1
25 MHz to 33.34 MHz 25 MHz to 33.34 MHz
H'0126 ON (× 4) OFF
2:1:1
25 MHz to 33.34 MHz 25 MHz to 33.34 MHz
H'012A ON (× 4) OFF
1:1:1
25 MHz to 33.34 MHz 25 MHz to 33.34 MHz
H'A100 ON (× 3) OFF
3:1:1
25 MHz to 33.34 MHz 25 MHz to 33.34 MHz
H'A101 ON (× 3) OFF
3:1:1/2
25 MHz to 44.44 MHz 25 MHz to 44.44 MHz
H'E100 ON (× 3) OFF
1:1:1
25 MHz to 33.34 MHz 25 MHz to 33.34 MHz
H'E101 ON (× 3) OFF
1:1:1/2
25 MHz to 44.44 MHz 25 MHz to 44.44 MHz
Notes: 1. This LSI cannot operate in an FRQCR value other than that listed in table 10.3.
2. Taking input clock as 1
Max. frequency: Iφ = 133.34 MHz, Bφ (CKIO) = 66.67 MHz, Pφ = 33.34 MHz
Cautions:
1. The input to divider 1 is the output of the PLL circuit 1:
• When PLL circuit 1 is on.
2. The input of divider 2 is the output of the PLL circuit 1.
3. The frequency of the CPU clock (Iφ):
• The frequency of the CPU clock (Iφ) is the product of the frequency of the CKIO pin,
the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 1
when PLL circuit 1 is on.
• Do not set the CPU clock frequency lower than the CKIO pin frequency.
4. The frequency of the peripheral clock (Pφ):
• The frequency of the peripheral clock (Pφ) is the product of the frequency of the CKIO
pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 2.
• The peripheral clock frequency should not be set higher than the frequency of the CKIO
pin, or higher than 33 MHz.
5. The output frequency of PLL circuit 1 is the product of the CKIO frequency and the
multiplication ratio of PLL circuit 1.
Rev. 5.00 May 29, 2006 page 309 of 698
REJ09B0146-0500