SH7706 Datasheet, PDF (262/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Table 8.17 Relationship between Bus Width, AMX, and Address Multiplex Output
Bus Memory
Width Type
Setting
Output
AMX3 AMX2 AMX1 AMX0 Timing
A1 to A8 A9
External Address Pins
A10 A11 A12 A13 A14 A15 A16
32 bits 4M ×
1
1
0
1
Column A1 to A8 A9
A10 A11 L/H^*3 A13 A23 A24^*4 A25^*4
16 bits ×
4 banks^*1
address
Row
A10 to A17 A18 A19 A20 A21 A22 A23 A24 A25^*4
address
2M ×
0
1
0
1
Column A1 to A8 A9
A10 A11 L/H^*3 A13 A23^*4 A24^*4
16 bits ×
4 banks^*2
address
Row
A10 to A17 A18 A19 A20 A21 A22 A23^*4 A24^*4
address
1M ×
0
1
0
0
Column A1 to A8 A9
A10 A11 L/H^*3 A13 A22^*4 A23^*4
16 bits ×
4 banks^*2
address
Row
A9 to A16 A17 A18 A19 A20 A21 A22^*4 A23^*4
address
2M ×
0
1
0
1
Column A1 to A8 A9
A10 A11 L/H^*3 A13 A23^*4 A24^*4
8 bits ×
4 banks^*2
address
Row
A10 to A17 A18 A19 A20 A21 A22 A23^*4 A24^*4
address
512k × 0
1
1
1
Column A1 to A8 A9
A10 A11 L/H^*3 A21^*4 A22^*4 A15
32 bits ×
4 banks^*2
address
Row
A9 to A16 A17 A18 A19 A20 A21^*4 A22^*4 A23
address
16 bits 8M ×
1
1
1
0
Column A1 to A8 A9
A10 L/H^*3 A12 A23 A24^*4 A25^*4
16 bits ×
4 banks^*1
address
Row
A11 to A18 A19 A20 A21 A22 A23 A24^*4 A25^*4
address
4M ×
1
1
0
1
Column A1 to A8 A9
A10 L/H^*3 A12 A22 A23^*4 A24^*4
16 bits ×
address
4 banks^*2
Row
A10 to A17 A18 A19 A20 A21 A22 A23^*4 A24^*4
address
2M ×
0
1
0
1
Column A1 to A8 A9
A10 L/H^*3 A12 A22^*4 A23^*4 A24
16 bits ×
4 banks^*2
address
Row
A10 to A17 A18 A19 A20 A21 A22^*4 A23^*4 A24
address
1M ×
0
1
0
0
Column A1 to A8 A9
A10 L/H^*3 A12 A21^*4 A22^*4 A15
16 bits ×
4 banks^*2
address
Row
A9 to A16 A17 A18 A19 A20 A21^*4 A22^*4 A23
address
2M ×
0
1
0
1
Column A1 to A8 A9
A10 L/H^*3 A12 A22^*4 A23^*4 A24
8 bits ×
4 banks^*2
address
Row
A10 to A17 A18 A19 A20 A21 A22^*4 A23^*4 A24
address
Notes: 1. Only RASL/CASL are output.
2. RASU and CASU are output for upper 32-Mbyte addresses, and RASL and CASL for lower 32-
Mbyte addresses.
3. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode.
4. Bank address specification
Rev. 5.00 May 29, 2006 page 214 of 698
REJ09B0146-0500