SH7706 Datasheet, PDF (264/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
The example in figure 8.13 shows the basic timing. To connect low-speed synchronous DRAM,
the cycle can be extended by setting WCR2 and MCR bits. The number of cycles from the ACTV
command output cycle, Tr, to the READ command output cycle, Tc1, can be specified by the
RCD bit in MCR, with a values of 0 to 3 specifying 1 to 4 cycles, respectively. In case of 2 or
more cycles, a Trw cycle, in which an NOP command is issued for the synchronous DRAM, is
inserted between the Tr cycle and the Tc cycle. The number of cycles from READ and READA
command output cycles Tc1-Tc4 to the first read data latch cycle, Td1, can be specified as 1 to 3
cycles independently for areas 2 and 3 by means of A2W1 and A2W0 or A3W1 and A3W0 in
WCR2. This number of cycles corresponds to the number of synchronous DRAM CAS latency
cycles.
Tr
Tc1
Tc2/Td1
Tc3/Td2
Tc4/Td3
Td4
Tpc
CKIO
Address
upper bits
A12 or A11^*1
Address
lower bits^*2
CS2 or CS3
RASx
CASx
RD/WR
DQMxx
D31 to D0
BS
Notes: 1. Command bit
2. Column address
Figure 8.13 Basic Timing for Synchronous DRAM Burst Read
Rev. 5.00 May 29, 2006 page 216 of 698
REJ09B0146-0500