SH7706 Datasheet, PDF (460/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 14 Serial Communication Interface (SCI)
Transmitting Serial Data (Clock Synchronous Mode): Figure 14.19 shows a sample flowchart
for transmitting serial data. Transmission of serial data should be carried out in the following
procedure after setting the SCI in a transmission-enabled state.
Start transmission
Read TDRE bit in SCSSR
No
TDRE = 1?
Yes
Write transmission data to SCTDR
and clear TDRE bit in SCSSR to 0
All data transmitted?
No
Yes
Read TEND bit in SCSSR
1. SCI status check and transmit data
write: Read the serial status register
(SCSSR), check that the TDRE bit is
1, then write transmit data in the
transmit data register (SCTDR) and
clear TDRE to 0.
2. To continue transmitting serial data:
Read the TDRE bit to check whether
it is safe to write (if it reads 1); if so,
write data in SCTDR, then clear
TDRE to 0.
TEND = 1?
No
Yes
Clear TE bit in SCSCR to 0
End transmission
Figure 14.19 Sample Flowchart for Serial Transmitting
Rev. 5.00 May 29, 2006 page 412 of 698
REJ09B0146-0500