SH7706 Datasheet, PDF (245/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
8.4.11 Refresh Count Register (RFCR)
The refresh count register (RFCR) is a 16-bit read/write register. It is a 10-bit counter that
increments every time RTCOR and RTCNT match. When RFCR exceeds the count limit value set
in the LMTS of RTCSR, RTCSR's OVF bit is set and RFCR clears. RFCR is initialized to H'0000
when a power-on reset is performed. It is not initialized by a manual reset or standby mode, but
holds its contents.
Note:
Writing to the RFCR differs from that to general registers to ensure the RFCR is not
rewritten incorrectly. Use the word-transfer instruction to set the MSB and followed six
bits of upper bytes as B'101001 and remaining bits as the write data. For the byte-transfer
instruction, writing is disabled. Read data in 16 bits. 0 is read from undefined bits.
Bit
Bit Name
15 to 10 —
Initial Value R/W
All 0
R
9 to 0 —
All 0
R/W
Description
Reserved
These bits are always read as 0.
10-bit counter
8.5 Operation
8.5.1 Endian/Access Size and Data Alignment
This LSI supports both big endian, in which the 0 address is the most significant byte in the byte
data, and little endian, in which the 0 address is the least significant byte. This switchover is
designated by an external pin (MD5 pin) at the time of a power-on reset. After a power-on reset,
big endian is engaged when MD5 is low; little endian is engaged when MD5 is high.
Three data bus widths are available for ordinary memory (byte, word, longword) and two data bus
widths (word and longword) for synchronous DRAM. For the PCMCIA interface, choose from
byte and word. This means data alignment is done by matching the device's data width and endian.
The access unit must also be matched to the device's bus width. This also means that when
longword data is read from a byte-width device, the read operation must happen 4 times. In this
LSI, data alignment and conversion of data length is performed automatically between the
respective interfaces.
Tables 8.11 through 8.16 show the relationship between endian, device data width, and access
unit.
Rev. 5.00 May 29, 2006 page 197 of 698
REJ09B0146-0500