SH7706 Datasheet, PDF (72/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 2 CPU
Addressing Instruction
Mode
Format Effective Address Calculation Method
Register
@(disp:4,
indirect with Rn)
displacement
Effective address is register Rn contents
with 4-bit displacement disp added.
After disp is zero-extended, it is multiplied
by 1 (byte), 2 (word), or 4 (longword),
according to the operand size.
Calculation Formula
Byte: Rn + disp
Word: Rn + disp × 2
Longword: Rn + disp ×
4
Rn
disp
+
(zero-extended)
×
Rn
+ disp × 1/2/4
Indexed
register
indirect
1/2/4
@(R0, Rn) Effective address is sum of register Rn and
R0 contents.
Rn
Rn + R0
+
Rn + R0
GBR indirect @(disp:8,
with
GBR)
displacement
R0
Effective address is register GBR contents
with 8-bit displacement disp added.
After disp is zero-extended, it is multiplied
by 1 (byte), 2 (word), or 4 (longword),
according to the operand size.
Byte: GBR + disp
Word: GBR + disp × 2
Longword: GBR + disp
×4
GBR
disp
+
(zero-extended)
×
GBR
+ disp × 1/2/4
Indexed
GBR
indirect
@(R0,
GBR)
1/2/4
Effective address is sum of register GBR
and R0 contents.
GBR + R0
GBR
+
GBR + R0
R0
Rev. 5.00 May 29, 2006 page 24 of 698
REJ09B0146-0500