SH7706 Datasheet, PDF (76/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 2 CPU
Instruction Format
Source
Operand
Destination
Operand
Instruction
Example
nm
15
0 mmmm: register nnnn: register ADD
format
xxxx nnnn mmmm xxxx direct
direct
Rm,Rn
mmmm: register nnnn: register MOV.L
indirect
indirect
Rm,@Rn
mmmm: register
indirect with post-
increment
(multiply-and-
accumulate
operation)
MACH,MACL
MAC.W
@Rm+,@Rn+
nnnn: * register
indirect with post-
increment
(multiply-and-
accumulate
operation)
mmmm: register nnnn: register
indirect with post- direct
increment
MOV.L
@Rm+,Rn
mmmm: register
direct
nnnn: register MOV.L
indirect with
Rm,@–Rn
pre-decrement
mmmm: register nnnn: indexed MOV.L
direct
register indirect Rm,@(R0,Rn)
md
format
15
xxxx
0 mmmmdddd:
R0 (register
xxxx mmmm dddd register indirect direct)
with displacement
MOV.B
@(disp,Rm),R0
nd4
format
15
0 R0 (register direct) nnnndddd:
MOV.B
xxxx xxxx nnnn dddd
register indirect R0,@(disp,Rn)
with
displacement
Rev. 5.00 May 29, 2006 page 28 of 698
REJ09B0146-0500