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SH7706 Datasheet, PDF (86/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series
Section 2 CPU
Instruction
Operation
Code
Privileged
Mode
Cycles T Bit
SUB Rm,Rn
Rn–Rm → Rn
0011nnnnmmmm1000 —
1
—
SUBC Rm,Rn
Rn–Rm–T → Rn,
Borrow → T
0011nnnnmmmm1010 —
1
Borrow
SUBV
Note:
Rm,Rn
Rn–Rm → Rn,
Underflow → T
0011nnnnmmmm1011 —
1
Underflow
* The normal number of execution cycles is shown. The value in parentheses is the
number of cycles required in case of contention with the preceding or following
instruction.
Rev. 5.00 May 29, 2006 page 38 of 698
REJ09B0146-0500