SH7706 Datasheet, PDF (314/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
Start
Initial settings
(SAR, DAR, DMATCR, CHCR, DMAOR)
DE, DME = 1 and
No
NMIF, TE = 0?
Yes
Transfer request
No
occurs?*¹
Yes
Transfer (1 transfer unit);
DMATCR – 1 → DMATCR, SAR and DAR
updated
*2
Bus mode,
*³
transfer request mode,
DREQ detection selection
system
No
DMATCR = 0?
Yes
DEI interrupt request (when IE = 1)
NMIF = 1 or
No
DE = 0 or DME
= 0?
Yes
Transfer aborted
NMIF = 1 or
No
DE = 0 or DME
= 0?
Yes
Transfer end
Normal end
Notes: 1. In auto-request mode, transfer begins when NMIF and TE are all 0 and the DE and DME bits
are set to 1.
2. DREQ = level detection in burst mode (external request) or cycle-steal mode.
3. DREQ = edge detection in burst mode (external request), or auto-request mode in burst mode.
Figure 9.2 DMAC Transfer Flowchart
Rev. 5.00 May 29, 2006 page 266 of 698
REJ09B0146-0500