SH7706 Datasheet, PDF (159/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 5 Cache
5.4.3 Usage Examples
1. Invalidating Specific Entries
Specific cache entries can be invalidated by writing 0 to the entry's U and V bit. When the A
bit is 1, the address tag specified by the write data is compared to the address tag within the
cache selected by the entry address, and data is written when a match is found. If no match is
found, there is no operation. When the V bit of the entry is 1, a write back occurs.
; R0=H'0110 0010; VPN=B'00 0000 0100 0100 0000 0000, U=0, V=0
; R1=H'F000 0088; address array access, entry=B'0000 1000, A=1
;
MOV.L R0,@R1
2. Reading the Data of a Specific Entry
This example reads the data section of a specific cache entry. The longword indicated in the
data field of the data array in figure 5.6 is read to the register.
; R1=H'F100 004C; data array access, entry=B'0000 0100, Way=0,
; longword address=3
;
MOV.L @R0,R1 ; Longword 3 is read.
Rev. 5.00 May 29, 2006 page 111 of 698
REJ09B0146-0500