SH7706 Datasheet, PDF (190/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 7 User Break Controller
7.2.2 Break Address Mask Register A (BAMRA)
BAMRA is a 32-bit read/write register. BAMRA specifies bits masked in the break address
specified by BARA.
Bit
31 to 0
Bit Name
BAMA31 to
BAMA0
Initial Value R/W
All 0
R/W
Note: n = 31 to 0.
Description
Break Address Mask Bit
Specifies bits masked in the channel A break
address bits specified by BARA (BAA31 to
BAA0).
0: Break address bit BAAn of channel A is
included in the break condition
1: Break address bit BAAn of channel A is
masked and is not included in the break
condition
7.2.3 Break Bus Cycle Register A (BBRA)
Break bus cycle register A (BBRA) is a 16-bit read/write register, which specifies (1) CPU cycle
or DMAC cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the
break conditions of channel A.
Rev. 5.00 May 29, 2006 page 142 of 698
REJ09B0146-0500