SH7706 Datasheet, PDF (307/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
Bit
Bit Name Initial Value R/W
Description
13
SM1
0
R/W
Source Address Mode
12
SM0
0
R/W
SM1 and SM0 select whether the DMA source
address is incremented, decremented, or left
fixed.
00: Fixed source address
01: Source address is incremented (+1 in 8-bit
transfer, +2 in 16-bit transfer, +4 in 32-bit
transfer, +16 in 16-byte transfer)
10: Source address is decremented (–1 in 8-bit
transfer, –2 in 16-bit transfer, –4 in 32-bit
transfer; illegal setting in 16-byte transfer)
11: Reserved (Setting prohibited)
Notes: If the transfer source is specified in indirect
address, specify the address, in which the
data to be transferred is stored and which
is stored as data (indirect address),
SAR_3.
Specification of SAR_3 increment or
decrement in indirect address mode
depends on SM1 and SM0 settings. In this
case, however, the SAR_3 increment or
decrement value is +4, –4, or fixed to 0
regardless of the transfer data size
specified in TS1 and TS0.
Rev. 5.00 May 29, 2006 page 259 of 698
REJ09B0146-0500