SH7706 Datasheet, PDF (147/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 5 Cache
Section 5 Cache
5.1 Feature
• Instruction/data mixed, 16-byte cache
• 256 entries/way, 4-way set associative, 16-byte block
• Write-back/write-through selectable
• LRU replacing algorithm
• 1-stage write-back buffer
• A maximum of two ways lockable
5.1.1 Cache Structure
The cache uses a 4-way set associative system. It is composed of four ways (banks), each of which
is divided into an address section and a data section. Each of the address and data sections is
divided into 256 entries. The data section of the entry is called a line. Each line consists of 16
bytes (4 bytes × 4). The data capacity per way is 4 kbytes (16 bytes × 256 entries), with a total of
16 kbytes in the cache as a whole (4 ways). Figure 5.1 shows the cache structure.
Address array (ways 0 to 3)
Data array (ways 0 to 3)
Entry 0 _{V U Tag address}
Entry 1
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0 _LW0
1
LW1
LW2
LW3
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LRU
0
1
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Entry 255
24 (1 + 1 + 22) bits
255
128 (32 × 4) bits
LW0 to LW3: Longword data 0 to 3
Figure 5.1 Cache Structure
255
6 bits
Rev. 5.00 May 29, 2006 page 99 of 698
REJ09B0146-0500