SH7706 Datasheet, PDF (198/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 7 User Break Controller
Bit
Bit Name Initial Value R/W Description
3
SEQ
0
R/W Sequence Condition Select
Selects two conditions of channels A and B as
independent or sequential.
0: Channels A and B are compared under the
independent condition
1: Channels A and B are compared under the
sequential condition
2, 1
—
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
ETBE
0
R/W The Number of Execution Times Break Enable
Enable the execution-times break condition only
on channel B. If this bit is 1 (break enable), a
user break is issued when the number of break
conditions matches with the number of execution
times that is specified by the BETR register.
0: The execution-times break condition is
masked on channel B
1: The execution-times break condition is
enabled on channel B
7.2.10 Execution Times Break Register (BETR)
When the execution-times break condition of channel B is enabled, this register specifies the
number of execution times to make the break. The maximum number is 2¹² – 1 times. Everytime
the break condition is satisfied, BETR is decremented by 1. A break is issued when the break
condition is satisfied after the BETR becomes H'0001.
Bit
Bit Name
15 to 12 —
11 to 0 —
Initial Value R/W
All 0
R
All 0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Number of execution times
Rev. 5.00 May 29, 2006 page 150 of 698
REJ09B0146-0500