SH7706 Datasheet, PDF (151/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 5 Cache
Bit
1
0
Note:
Bit Name Initial Value R/W Description
W2LOAD 0
W
W3LOAD: Way 2 load
W2LOCK 0
W
W3LOCK: Way 2 Lock
When W3LOACK = 1 & W3LOAD = 1 & SR.CL is
1, the prefetched data will always be loaded into
Way2. In all other conditions, the prefetched data
will be loaded into the way pointed by LRU.
Do not set 1 into W2LOAD and W3LOAD at the same time.
Whenever CCR2 bit 8 (W3LOCK) or bit 0 (W2LOCK) is high level the cache is locked. The
locked data will not be overwritten unless W3LOCK bit and W2LOCK bit are reset or the PREF
condition during cache locking mode watches. During cache locking mode, the LRU in table 5.1
will be replaced by tables 5.4 to 5.6.
Table 5.2 Way to be Replaced when Cache Miss Occurs during PREF Instruction
Execution
CL bit W3LOAD W3LOCK W2LOAD W2LOCK Way to be Replaced
0
*
*
*
*
According to LRU (table 5.1)
1
*
0
*
0
According to LRU (table 5.1)
1
*
0
0
1
According to LRU (table 5.4)
1
0
1
*
0
According to LRU (table 5.5)
1
0
1
0
1
According to LRU (table 5.6)
1
0
*
1
1
Way 2
1
1
1
0
*
Way 3
Legend: * Don't care
Note: Do not set 1 into W2LOAD and W3LOAD at the same time.
Rev. 5.00 May 29, 2006 page 103 of 698
REJ09B0146-0500