SH7706 Datasheet, PDF (194/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 7 User Break Controller
Bit
Bit Name Initial Value R/W
5
IDB1
0
R/W
4
IDB0
0
R/W
3
RWB1
0
R/W
2
RWB0
0
R/W
1
SZB1
0
R/W
0
SZB0
0
R/W
Legend: X: Don't care
Description
Instruction Fetch/Data Access Select B
Select the instruction fetch cycle or data access
cycle as the bus cycle of the channel B break
condition.
00: Condition comparison is not performed
01: The break condition is the instruction fetch cycle
10: The break condition is the data access cycle
11: The break condition is the instruction fetch cycle
or data access cycle
Read/Write Select B
Select the read cycle or write cycle as the bus cycle
of the channel B break condition.
00: Condition comparison is not performed
01: The break condition is the read cycle
10: The break condition is the write cycle
11: The break condition is the read cycle or write
cycle
Operand Size Select B
Select the operand size of the bus cycle for the
channel B break condition.
00: The break condition does not include operand
size
01: The break condition is byte access
10: The break condition is word access
11: The break condition is longword access
Rev. 5.00 May 29, 2006 page 146 of 698
REJ09B0146-0500