SH7706 Datasheet, PDF (500/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.7 Serial Status Register 2 (SCSSR2)
The serial status register 2 (SCSSR2) is a 16-bit register. The upper 8 bits indicate the number of
receive errors in the data of the SCFRDR2, and the lower 8 bits indicate SCIF operating state.
The CPU can always read and write the SCSSR2, but cannot write 1 to the status flags (ER,
TEND, TDFE, BRK, OPER, and DR). These flags can be cleared to 0 only if they have first been
read (after being set to 1). Bits 3 (FER) and 2 (PER) are read-only bits and cannot be written.
Bit
15 to
12
Bit Name
PER3 to
PER0
Initial
Value R/W
All 0 R
11 to FER3 to
8
FER0
All 0 R
Description
Number of parity errors
These bits indicate the number of data items that contain a
parity error in the receive data stored in the SCFRDR2.
(The number of parity errors in the SCFRDR2)
Number of framing errors
These bits indicate the number of data items that contain a
framing error in the receive data stored in the SCFRDR2.
(The number of framing errors in the SCFRDR2)
Rev. 5.00 May 29, 2006 page 452 of 698
REJ09B0146-0500