SH7706 Datasheet, PDF (302/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
9.2 Input/Output Pin
Table 9.1 shows the DMAC pins.
Table 9.1 Pin Configuration
Channel Name
0
DMA transfer request
Symbol
DREQ0
DREQ acknowledge DACK0
DMA request
acknowledge
DRAK0
1
DMA transfer request DREQ1
DREQ acknowledge DACK1
DMA request
acknowledge
DRAK1
I/O Function
I
DMA transfer request input from
external device to channel 0
O Strobe output to an external I/O at DMA
transfer request from external device to
channel 0
O Output showing that DREQ0 has been
accepted
I
DMA transfer request input from
external device to channel 1
O Strobe output to an external I/O at DMA
transfer request from external device to
channel 1
O Output showing that DREQ1 has been
accepted
9.3 Register Description
DMAC has a total of 17 registers. Each channel has four control registers. One other control
register is shared by all channels.
Refer to section 23, List of Registers, for more details of the addresses and access sizes.
Channel 0
• DMA source address register 0 (SAR0)
• DMA destination address register 0 (DAR0)
• DMA transfer count register 0 (DMATCR0)
• DMA channel control register 0 (CHCR0)
Channel 1
• DMA source address register 1 (SAR1)
• DMA destination address register 1 (DAR1)
• DMA transfer count register 1 (DMATCR1)
• DMA channel control register 1 (CHCR1)
Rev. 5.00 May 29, 2006 page 254 of 698
REJ09B0146-0500