SH7706 Datasheet, PDF (236/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Bit Bit Name Initial Value R/W Description
6
AMX3
0
R/W Address Multiplex
5
AMX2
0
4
AMX1
0
3
AMX0
0
R/W The AMX bits specify address multiplexing for
R/W ^{synchronous DRAM. The actual address shift value}
differs between DRAM interface and synchronous
R/W _{DRAM interface.}
For Synchronous DRAM interface:
0000: Reserved (Setting prohibited)
0001: Reserved (Setting prohibited)
0010: Reserved (Setting prohibited)
0011: Reserved (Setting prohibited)
0100: The row address begins with A9. (The A9
value is output at A1 when the row address is
output. 64 M (1 M × 16 bits × 4 banks))
0101: The row address begins with A10. (The A10
value is output at A1 when the row address is
output. 128 M (2 M × 16 bits × 4 banks), 64 M
(2 M × 8 bits × 4 banks))
0110: Cannot be set.
0111: The row address begins with A9. (The A9
value is output at A1 when the row address is
output. 64 M (512 k × 32 bits × 4 banks)^*2)
1000: Reserved (Setting prohibited)
1001: Reserved (Setting prohibited)
1010: Reserved (Setting prohibited)
1011: Reserved (Setting prohibited)
1100: Reserved (Setting prohibited)
1101: The row address begins with A10. (The A10
value is output at A1 when the row address is
output. 256 M (4 M × 16 bits × 4 banks))
1110: The row address begins with A11. (The A11
value is output at A1 when the row address is
output. 512 M (8 M × 16 bits × 4 banks)^*1)
1111: Reserved (Setting prohibited)
Notes: 1. Cannot be set when using a 32-bit bus
width.
2. Cannot be set when using a 16-bit bus
width.
Rev. 5.00 May 29, 2006 page 188 of 698
REJ09B0146-0500