SH7706 Datasheet, PDF (24/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

3.3.3 TLB Address Comparison ................................................................................... 63
3.3.4 Page Management Information............................................................................ 65
3.4 MMU Functions................................................................................................................ 66
3.4.1 MMU Hardware Management ............................................................................. 66
3.4.2 MMU Software Management .............................................................................. 66
3.4.3 MMU Instruction (LDTLB)................................................................................. 67
3.4.4 Avoiding Synonym Problems .............................................................................. 68
3.5 MMU Exceptions.............................................................................................................. 70
3.5.1 TLB Miss Exception ............................................................................................ 70
3.5.2 TLB Protection Violation Exception ................................................................... 71
3.5.3 TLB Invalid Exception ........................................................................................ 72
3.5.4 Initial Page Write Exception ................................................................................ 73
3.5.5 Processing Flow in Event of MMU Exception
(Same Processing Flow for CPU Address Error)................................................. 75
3.6 Configuration of the Memory-Mapped TLB .................................................................... 77
3.6.1 Address Array ...................................................................................................... 77
3.6.2 Data Array............................................................................................................ 77
3.6.3 Usage Examples................................................................................................... 79
3.7 Usage Note........................................................................................................................ 79
3.7.1 Use of Instructions Manipulating MD and BL Bits in SR ................................... 79
3.7.2 Use of TLB .......................................................................................................... 80
Section 4 Exception Processing....................................................................................... 81
4.1 Exception Processing Function ......................................................................................... 81
4.1.1 Exception Processing Flow.................................................................................. 81
4.1.2 Exception Processing Vector Addresses.............................................................. 82
4.1.3 Acceptance of Exceptions.................................................................................... 83
4.1.4 Exception Codes .................................................................................................. 85
4.1.5 Exception Request and BL Bit............................................................................. 86
4.1.6 Returning from Exception Processing ................................................................. 86
4.2 Register Description.......................................................................................................... 87
4.2.1 Exception Event Register (EXPEVT).................................................................. 87
4.2.2 Interrupt Event Register (INTEVT) ..................................................................... 88
4.2.3 Interrupt Event Register 2 (INTEVT2) ................................................................ 88
4.2.4 TRAPA Exception Register (TRA) ..................................................................... 89
4.3 Operation .......................................................................................................................... 89
4.3.1 Reset..................................................................................................................... 89
4.3.2 Interrupts.............................................................................................................. 90
4.3.3 General Exceptions .............................................................................................. 90
4.4 Individual Exception Operations....................................................................................... 91
4.4.1 Resets ................................................................................................................... 91
Rev. 5.00 May 29, 2006 page xxiv of xlviii