SH7706 Datasheet, PDF (586/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 19 A/D Converter (ADC)
19.5 Access Size of A/D Data Register
19.5.1 Word Access
When A/D data registers (ADDRA to ADDRD) are read in word, A/D data register values are
read from bits 15 to 8, and invalid data is read from bits 7 to 0.
Figure 19.3 shows an example of reading ADDRAH.
15
87
0
ADDRAH
Invalid data
Figure 19.3 Word Access Example
19.5.2 Longword Access
When A/D data registers are read in longword, the upper byte of the A/D data register is read from
bits 31 to 24, invalid data from bits 23 to 16, the lower byte of the A/D data register from bits 15
to 8, and invalid data from bits 7 to 0.
Figure 19.4 shows an example of reading ADDRAH.
31
24 23
16 15
87
0
ADDRAH
Invalid data
ADDRAL
Invalid data
Figure 19.4 Longword Access Example
Rev. 5.00 May 29, 2006 page 538 of 698
REJ09B0146-0500