SH7706 Datasheet, PDF (64/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 2 CPU
2.1.3 System Registers
System registers can be accessed by the LDS and STS instructions. When an exception occurs, the
contents of the program counter (PC) are saved in the saved program counter (SPC). The SPC
contents are restored to the PC by the RTE instruction used at the end of the exception handling.
There are three system registers, as follows.
• Multiply and accumulate register (MAC)
• Procedure register (PR)
• Program counter (PC)
The system register configuration is shown in figure 2.3.
Multiply and Accumulate Register (MAC)
31
0
MACH
MACL
Procedure Register (PR)
31
0
PR
Program Counter (PC)
31
0
PC
Figure 2.3 System Registers
1. Multiply and Accumulate Register (MAC)
Multiply and Accumulate register is consist of Higher part register (MACH) and Lower part
register (MACL).
Store the results of multiply-and-accumulate operations.
Initialized to undefined by a reset.
2. Procedure Register (PR)
Stores the return address for exiting a subroutine procedure.
Initialized to undefined by a reset.
3. Program Counter (PC)
Indicates the address four addresses (two instructions) ahead of the currently executing
instruction. Initialized to H'A0000000 by a reset.
Rev. 5.00 May 29, 2006 page 16 of 698
REJ09B0146-0500