SH7706 Datasheet, PDF (358/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 10 Clock Pulse Generator (CPG)
6. × 1, × 2, × 3, or × 4 can be used as the multiplication ratio of PLL circuit 1. × 1, × 1/2, × 1/3,
and × 1/4 can be selected as the division ratios of dividers 1 and 2. Set the rate in the frequency
control register. The on/off state of PLL circuit 2 and the multiplication ratio are determined by
the mode.
10.4 Register Description
The CPG includes the following register. Refer to section 23, List of Registers, for more details of
the addresses and access sizes.
• Frequency control register (FRQCR)
10.4.1 Frequency Control Register (FRQCR)
The frequency control register (FRQCR) is a 16-bit read/write register used to specify, the
frequency multiplication ratio of PLL circuit 1, and the frequency division ratio of the CPU clock
and the peripheral clock. Only word access can be used on the FRQCR register.
The FRQCR register is initialized to H'0102 at a power-on reset by the RESETP pin and retains its
previous value at a manual reset or in standby mode.
Bit
Bit Name Initial Value R/W Description
15
STC2
0
R/W Frequency Multiplication Ratio
5
STC1
0
4
STC0
0
R/W These bits specify the frequency multiplication ratio
R/W ^{of PLL circuit 1.}
000: × 1
001: × 2
100: × 3
010: × 4
Other than the above: Reserved (Setting prohibited)
Note: Do not set the output frequency of PLL circuit
1 higher than 133 MHz.
Rev. 5.00 May 29, 2006 page 310 of 698
REJ09B0146-0500