SH7706 Datasheet, PDF (289/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Memory Card Interface Burst Timing: In this LSI, when the IC memory card interface is
selected, page mode burst access mode can be used, for read access only, by setting bits A5BST1
and A5BST0 in BCR1 for physical space area 5, or bits A6BST1 and A6BST0 in BCR1 for area
6. This burst access mode is not stipulated in JEIDA version 4.2 (PCMCIA2.1), but allows high-
speed data access using ROM provided with a burst mode, etc.
Burst access mode timing is shown in figures 8.34 and 8.35.
CKIO
Tpcm1 Tpcm2 Tpcm1 Tpcm2 Tpcm1 Tpcm2 Tpcm1 Tpcm2
A25 to A4
A3 to A0
CExx
RD/WR
RD
(read)
D15 to D0
(read)
BS
Figure 8.34 Basic Timing for PCMCIA Memory Card Interface Burst Access
Rev. 5.00 May 29, 2006 page 241 of 698
REJ09B0146-0500