SH7706 Datasheet, PDF (678/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 24 Electrical Characteristics
24.3.6 Synchronous DRAM Timing
CKIO
A25 to A16
A12 or A11
A15 to A0
CSn
RD/WR
RAS
CAS
DQMxx
D31 to D0
BS
Tr
Tc1
Tc2
(Tpc)
t_AD
Row address
t_AD
t_AD
t_AD
Row address
t_AD
t_AD
Read A
command
Row address
t_CSD3
Column address
t_AD
t_AD
t_CSD3
t_RWD
t_RWD
t_RASD
t_RASD
t_CASD
t_CASD
t_DQMD
t_DQMD
t_RDS2 t_RDH2
t_BSD
t_BSD
CKE
DACKn
t_DAKD1
(High)
t_DAKD1
Figure 24.22 Synchronous DRAM Read Bus Cycle (RCD = 0, CAS Latency = 1, TPC = 0)
Rev. 5.00 May 29, 2006 page 630 of 698
REJ09B0146-0500