SH7706 Datasheet, PDF (345/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
Peripheral clock (Pφ)
CMCNT input clock
CMCNT
N
0
CMCOR
N
Compare match signal
CMF
CMI
Figure 9.29 CMF Set Timing
Compare Match Flag Clear Timing
The CMF bit of the CMCSR register is cleared by writing 0 to it after reading 1. Figure 9.30
shows the timing when the CMF bit is cleared by the CPU.
CMCSR0 write cycle
T₁
T₂
Peripheral clock (Pφ)
CMF
Figure 9.30 Timing of CMF Clear by the CPU
Rev. 5.00 May 29, 2006 page 297 of 698
REJ09B0146-0500