SH7706 Datasheet, PDF (368/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 11 Watchdog Timer (WDT)
11.3.2 Changing the Frequency
To change the frequency used by the PLL, use the WDT. When changing the frequency only by
switching the divider, do not use the WDT.
1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit
is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows.
2. Set the type of count clock used in the CKS2 to CKS0 bits of WTCSR and the initial values for
the counter in the WTCNT counter. These values should ensure that the time till count
overflow is longer than the clock oscillation settling time.
3. When the frequency control register (FRQCR) is written, the clock stops and the processor
enters standby mode temporarily. The WDT starts counting.
4. When the WDT count overflows, the CPG resumes supplying the clock and the processor
resumes operation. The WOVF flag in WTCSR is not set when this happens.
5. The counter stops at the values H'00 to H'01. The stop value depends on the clock ratio.
6. Confirm that the value of WTCNT is H’00 before writing WTCNT, when WTCNT is written
after the frequency change.
11.3.3 Using Watchdog Timer Mode
1. Set the WT/IT bit in the WTCSR register to 1, set the reset type in the RSTS bit, set the type of
count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT
counter.
2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode.
3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent
the counter from overflowing.
4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1 and generates the
type of reset specified by the RSTS bit. The counter then resumes counting.
When a reset occurs, and a high level is output from the STATUS0 and STATUS1 pins. The
signal output period is about one cycle of the count clock for power-on reset, and about five
cycles of the peripheral clock for manual reset.
Rev. 5.00 May 29, 2006 page 320 of 698
REJ09B0146-0500