SH7706 Datasheet, PDF (430/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 14 Serial Communication Interface (SCI)
14.3.9 SC Port Data Register (SCPDR)
The SC port data register (SCPDR) controls data on the SCI and SCIF pins. The data controls on
the SCI and SCIF pins are performed using bits 1 and 0, and bits 5 and 2 in SCPDR, respectively.
Bit Bit Name Initial Value R/W Description
7, 6 

R
Reserved
These bits are always read as 0; only 0 should be
written here.
5
SCP5DT 
4
SCP4DT 0
R
See section 18.10.2, SC Port Data Register
R/W ^(SCPDR).
3
SCP3DT 0
R/W
2
SCP2DT 0
R/W
1
SCP1DT 0
R/W Serial clock port data
Specifies the serial port SCK0 pin I/O data. Input or
output is specified by the SCP1MD0 and SCP1MD1
bits. In output mode, the value of the SCP1DT bit is
output to the SCK0 pin.
0: I/O data is low (0).
1: I/O data is high (1).
0
SCP0DT 0
R/W Serial port break data
Specifies the serial port RxD0 pin input data and
TxD0 pin output data. The TxD0 pin output condition
is specified by the SCP0MD0 and SCP0MD1 bits.
When the TxD0 pin is set to output mode, the value
of the SCP0DT bit is output to the TxD0 pin. The
RxD0 pin value is read from the SCP0DT bit
regardless of the values of the SCP0MD0 and
SCP0MD1 bits, if RE in the SCSCR is set to 1. The
initial value of this bit after a power-on reset is
undefined.
0: I/O data is low (0).
1: I/O data is high (1).
Rev. 5.00 May 29, 2006 page 382 of 698
REJ09B0146-0500