SH7706 Datasheet, PDF (234/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
8.4.5 Individual Memory Control Register (MCR)
The individual memory control register (MCR) is a 16-bit read/write register that specifies RAS
and CAS timing and burst control for synchronous DRAM (areas 2 and 3), specifies address
multiplexing, and controls refresh. This enables direct connection of synchronous DRAM without
external circuits.
The MCR is initialized to H'0000 by power-on resets, but is not initialized by manual resets or
standby mode. The bits TPC1, TPC0, RCD1, RCD0, TRWL1, TRWL0, TRAS1, TRAS0, RASD
and AMX3 to AMX0 are written to at the initialization after a power-on reset and are not then
modified again. When RFSH and RMODE are written to, write the same values to the other bits.
When using synchronous DRAM, do not access areas 2 and 3 until this register is initialized.
Bit Bit Name Initial Value R/W Description
15 TPC1
0
R/W RAS Precharge Time
14 TPC0
0
R/W When synchronous DRAM interface is selected as
connected memory, they set the minimum number of
cycles until output of the next bank-active command
after precharge.
The number of cycles to be inserted immediately
after issuing a precharge all banks (PALL) command
in auto-refresh or a precharge (PRE) command in
bank-active mode is one cycle less than the normal
value. In bank-active mode, neither TPC1 nor TPC0
should be cleared to 0.
Normal
Operation
Immediately after* Immediately
Precharge
after
Command
Self-Refresh
00: 1 cycle
0 cycle
2 cycles
01: 2 cycles
1 cycle
5 cycles
10: 3 cycles
2 cycles
8 cycles
11: 4 cycles
3 cycles
11 cycles
Note: * Immediately after a precharge all banks (PALL)
command in auto-refresh and a precharge (PRE)
command in bank-active mode.
Rev. 5.00 May 29, 2006 page 186 of 698
REJ09B0146-0500