SH7706 Datasheet, PDF (139/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 4 Exception Processing
4.4 Individual Exception Operations
This section describes the conditions for specific exception processing, and the processor
operations.
4.4.1 Resets
• Power-On Reset
 Conditions: RESETP low
 Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000.
Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to
1 and the interrupt mask bits (I3 to I0) are set to B'1111. The CPU and on-chip supporting
modules are initialized. For details, refer to section 23, List of Registers. A power-on reset
must always be performed when powering on.
A high level is output from the STATUS0 and STATUS1 pins.
• Manual Reset
 Conditions: RESETM low
 Operations: EXPEVT set to H'020, VBR and SR initialized, branch to PC = H'A0000000.
Initialization sets the VBR register to H'0000000. In SR, the MD, RB, and BL bits are set
to 1 and the interrupt mask bits (I3 to I0) are set to B'1111. The CPU and on-chip
supporting modules are initialized. For details, refer to section 23, List of Registers.
A high level is output from the STATUS0 and STATUS1 pins.
• H-UDI Reset
 Conditions: H-UDI reset command input (see section 21, User Debugging Interface (H-
UDI))
 Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000.
Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to
1 and the interrupt mask bits (I3 to I0) are set to B'1111. The CPU and on-chip supporting
modules are initialized. For details, refer to section 23, List of Registers.
Rev. 5.00 May 29, 2006 page 91 of 698
REJ09B0146-0500