SH7706 Datasheet, PDF (155/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 5 Cache
5.3.3 Prefetch Operation
Prefetch Hit: LRU is updated so that the way that has been hit to be the latest. Other contents of
the cache are not updated. Instruction or data is not transferred to the CPU.
Prefetch Miss: Instruction or data is not transferred to the CPU. The way to be replaced is listed
in table 5.2. Other operations are same as those in read miss.
5.3.4 Write Access
Write Hit: In a write access in the write-back mode, the data is written to the cache and the U bit
of the entry written is set to 1. Writing occurs only to the cache; no external memory write cycle is
issued. In the write-through mode, the data is written to the cache and an external memory write
cycle is issued.
Write Miss: In the write-back mode, an external write cycle starts when a write miss occurs, and
the entry is updated. The way to be replaced is shown in table 5.3. When the U bit of the entry to
be replaced is 1, the cache fill cycle starts after the entry is transferred to the write-back buffer.
The write-back unit is 16 bytes. Data is written to the cache and the U bit and V bit are set to 1.
After the cache completes its fill cycle, the write-back buffer writes back the entry to the memory.
In the write-through mode, no write to cache occurs in a write miss; the write is only to the
external memory.
5.3.5 Write-Back Buffer
When the U bit of the entry to be replaced in the write-back mode is 1, it must be written back to
the external memory. To increase performance, the entry to be replaced is first transferred to the
write-back buffer and fetching of new entries to the cache takes priority over writing back to the
external memory. After fetching of new entries to the cache is completed, the data in the write-
back buffer is write back to the external memory. During the write back cycles, the cache can be
accessed. The write-back buffer can hold one line of the cache data (16 bytes) and its physical
address. Figure 5.3 shows the configuration of the write-back buffer.
PA (31 to 4) Longword 0 Longword 1 Longword 2 Longword 3
PA (31 to 4): Physical address written to external memory
Longword 0 to 3: The line of cache data to be written to
external memory
Figure 5.3 Write-Back Buffer Configuration
Rev. 5.00 May 29, 2006 page 107 of 698
REJ09B0146-0500