SH7706 Datasheet, PDF (283/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
CKIO
T1
TW
TW
TB2
TB1
TW
TB2 TB1
T2
A25 to A4
A3 to A0
CSn
RD/WR
RD
D31 to
D0
BS
WAIT
Note: For a write cycle, a basic bus cycle (write cycle) is performed.
Figure 8.28 Burst ROM Wait Access Timing
Rev. 5.00 May 29, 2006 page 235 of 698
REJ09B0146-0500